The present invention relates to a semiconductor integrated circuit device, and also relates to a technique capable of being applied to detection of a failure of a microcontroller, which is a computer for control.
A microcontroller is a device which is incorporated in equipment, such as household appliance, AV equipment, mobile telephone, automobile, and industrial machine and which performs control of each piece of equipment by performing processing in accordance with programs stored in a built-in memory, and the microcontroller is usually configured as a semiconductor integrated circuit.
In a part of equipment such as an automobile, high reliability is required for parts including the microcontroller because a failure of a control device may lead to an accident, and also the parts are designed so that the safety function is operated to prevent the equipment from reaching a dangerous state by detecting a failure when it occurs. It is necessary for the microcontroller not only to detect a failure of a sensor and actuator by diagnosing them, but also to detect a failure of the microcontroller itself.
Among a variety of methods for detecting a failure of a microcontroller, there is frequently used a method in which duplexed functional blocks (for example, CPU, which is a central operation unit (also called a central processing unit, central operation processing unit), hereinafter, the central operation unit is represented as CPU) having the same function are provided, and a failure of the functional block is detected by comparing output signals of each functional block. This detection method is called duplexing processing. The effectiveness of this method is based on the assumption that failures of the duplexed functional blocks occur independently and the same failure does not occur at the same time. In the case where the same failure has occurred in both the functional blocks at the same time, the erroneous outputs agree with each other, and thus it is not possible to detect the failure.
Japanese Patent Laid-Open No. 08-171581 (Patent Document 1) discloses a method for diversifying the design data of duplexed functional blocks, operation timings, and arrangement on the chip, in order to prevent occurrence of the same failure described above.
Furthermore, a method of using one or two CPUs to perform duplexing processing by two threads is disclosed in Japanese Patent No. 4531060 (Patent Document 2) and Japanese Patent Laid-Open No. 2011-44078 (Patent Document 3).